`timescale 1ns / 1ns

module led(
    input wire sys_clk,
    output reg[3:0] led
    );
    
    reg[31:0] time_cnt;
    
    initial 
    begin 
        led <= 4'b1111;
        time_cnt <= 32'd0;
    end 
    
    always @(posedge sys_clk)
    begin 
        if(time_cnt >= 32'd24_999_999)
        begin 
            led <= ~led;
            time_cnt <= 32'd0;
        end
        else
        begin 
            led <= led;
            time_cnt <= time_cnt + 32'd1;
        end
    end     

endmodule
